Net(; name = "", suffixes = [""], value = missing,
      type = :wire, class = :internal, signed = false,
      bitwidth = 1, size = (1, 1))
Net(x; kwargs...)

Create a new multi-dimensional SystemVerilog net (for x).

Arguments

• name::String: the name of the net (this can be a SystemVerilog constant expression too)
• suffixes::Vector{String}: set if this net represents multiple wires with suffixes (e.g. a signed stochastic bitstream has suffixes _p and _m)
• value: the underlying Julia value that this net represents
• type::Symbol: one of [:logic] (a SystemVerilog type)
• class::Symbol: one of [:input, :output, :internal, :constant, :parameter]
• signed::Bool: set true if the net is signed in SystemVerilog
• bitwidth::Int: the bit width of each element in the net
• size::Tuple{Int, Int, ...}: the size of the net in terms of number of elements

If x is specified, then value = x and size = netsize(x). netsize is like Base.size, but it expands scalars and vectors to 2D sizes (e.g. (1, 1)) If x is a SBitstream or AbstractArray{<:SBitstream}, then suffixes = ["_p", "_m"].