CircuitModule(fn; kwargs...)

A data structure to store information to generate hardware for fn.

Hardware generation traverses dfg and uses handlers to generate Verilog strings.

Keywords:

• name::Symbol: the name of the module (defaults to nameof(fn))
• bitwidth::@NamedTuple{integral::Int, fractional::Int}: the maximum bit width in the circuit
• parameters::Dict{String, Number}: a map from the name of each parameter to its default value
• submodules::Vector{Type}: a list of submodule types
• dfg::MetaDiGraph{Int, Float64}: a data flow graph representing the circuit to be generated
• handlers::Dict{Operation, AbstractHandler}: a map from operation type to a hardware generation handler and state